1. Field of the Invention
The present invention relates to packaging processes, and more particularly, to a package structure and a method for fabricating the same.
2. Description of Related Art
Along with the progress of semiconductor packaging technologies, a variety of package types have been developed for semiconductor devices. To improve electrical performances and save spaces, a plurality of packages can be stacked to form a package on package (POP) structure or a package in package (PIP) structure. Such a packaging method allows integration of heterogeneous technologies in a system-in-package (SiP) so as to systematically integrate a plurality of electronic elements having different functions, such as a memory, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an image application processor and so on, and therefore is applicable to various thin type electronic products.
FIG. 3 is schematic cross-sectional view of a conventional POP structure.
Referring to FIG. 3, a second package 3b is stacked on a first package 3a to form a POP structure 3.
The first package 3a has a first chip carrier 31 having opposite first and second surfaces 31a, 31b, and a first electronic element 30 disposed on the first surface 31a of the first chip carrier 31 and electrically connected to the first chip carrier 31. The second package 3b has a second chip carrier 32 having opposite third and fourth surfaces 32a, 32b, at least a second electronic element 35 disposed on the third surface 32a of the second chip carrier 32 and electrically connected to the second chip carrier 32, and an encapsulant 36 formed on the second chip carrier 32 for encapsulating the second electronic element 35. Further, a plurality of solder balls 310 are formed on the first surface 31a of the first chip carrier 31 and the second chip carrier 32 is stacked on the solder balls 310 via the fourth surface 32b thereof so as to be electrically connected to the first chip carrier 31. A plurality of conductive pads 312 are formed on the second surface 31b of the first chip carrier 31 for mounting solder balls 34. The first and second electronic elements 30, 35 can be active and/or passive elements. The first electronic element 30 is electrically connected to the first chip carrier 31 in a flip-chip manner, and the second electronic elements 35 is electrically connected to the second chip carrier 32 in a flip-chip manner. An underfill 33 is further filled between the first electronic element 30 and the first chip carrier 31 and between the second electronic element 35 and the second chip carrier 32 to form flip-chip bondings.
However, the POP structure 3 has a big size and cannot meet the miniaturization requirement. For example, the solder balls 310 are required to have a certain pitch therebetween so as to prevent bridging from occurring, thus making it difficult to reduce the size of the first chip carrier 31.
On the other hand, 3D IC chip stacking technologies have been developed. For example, a silicon interposer having a plurality of through silicon vias (TSVs) is disposed between a packaging chip carrier and at least a semiconductor chip. Since the silicon interposer can have a wire diameter/pitch of 3/3 um or less, the semiconductor chips having high I/O counts can be disposed on the silicon interposer without the need to increase the area of the packaging chip carrier, thereby meeting the miniaturization requirement.
However, to form the TSVs of the silicon interposer, a plurality of through holes need to be formed in the silicon interposer through a patterning process such as exposure, development and etching and then filled with metal, which incurs a high cost. For example, for a 12-inch wafer, the TSV cost is about 40 to 50% of the total cost for fabricating the silicon interposer (not including labor cost). Further, the fabrication process of the TSVs is time-consuming, especially when the silicon interposer is etched to form the through holes. Consequently, the final product increase in cost.
Therefore, there is a need to provide a package structure and a method for fabricating the same so as to overcome the above-described drawbacks.